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This page provides details on building and customizing the FSBL for Zynq UltraScale+ MPSoC, and of import notes on the FSBL. All the information is presented in the format of FAQs.

Tabular array of Contents

What is FSBL?

Starting time Ste FPGA with hardware bitstream (if it exists) and loads the Operating Arrangement (Bone) Image or Standalone (SA) Epitome or 2nd Stage Kicking Loader image from the not-volatile memory (NAND/SD/eMMC/QSPI) to Memory (DDR/TCM/OCM) and takes A53/R5 out of reset. It supports multiple partitions, and each division can be a code paradigm or a bitstream. Each of these partitions, if required, will exist authenticated and/or decrypted.
FSBL is loaded into OCM and handed off past CSU BootROM afterwards authenticating and/or decrypting (equally required) FSBL.

How to create FSBL from Vitis?

Launch VITIS with the below command: vitis
Provide path where VITIS workspace and project demand to be created. With this VITIS workspace will be created
(Optional footstep) To piece of work with local repos, Select "Xilinx" (ALT - 10) -> Repositories. Against Local Repositories, click on "New..." and provide path of the local repo
Select File-->New-->Application Project to open "New Project" window, provide name for FSBL project
In the "Platform" department, click on " (e.g. zcu102).

Alternatively, to create a new/custom platform from a .xsa file, click on "+", scan and select the XSA file and a new hardware platform is created.

In the "Domain" window, select the processor psu_cortexa53_0/psu_cortexr5_0, OS as standalone and Linguistic communication as C
Click Side by side and select "Zynq MP FSBL"
Click "Finish" to generate the A53/R5 FSBL. This populates the FSBL code and likewise builds it (along with BSP)
Debug prints in FSBL are now disabled by default (except for FSBL banner). To enable debug prints, ascertain symbol: FSBL_DEBUG_INFO

In VITIS this can be done past: right click on FSBL application projection -> select "C/C++ Build Settings" -> "Tool Settings" tab -> Symbols (under ARM v8 gcc compiler)
Click on Add (+) icon and Enter Value: FSBL_DEBUG_INFO, click on "OK" to close the "Enter Value" screen

In case any of the source files (FSBL or BSP) need to be modified, browse the file, make the change and relieve the file, build the project. elf file will exist present in the Debug/Release binder of FSBL projection.

What are various levels of debug prints in FSBL?

FSBL supports four levels of debug prints:

Type or prints	Purpose	Enabled by defining.. in FSBL lawmaking	Alternative way of enabling by defining symbol..
Ever	Used for prints, which should be always enabled (due east.one thousand. FSBL banner)	FSBL_PRINT_VAL to (1U)	FSBL_PRINT
DEBUG General	To print errors and basic general information	FSBL_DEBUG_VAL to (1U)	FSBL_DEBUG
DEBUG INFO	To have more prints with format specifiers, in addition to basic full general information	FSBL_DEBUG_INFO_VAL to (1U)	FSBL_DEBUG_INFO
DEBUG DETAILED	To take more detailed prints, in improver to higher up prints	FSBL_DEBUG_DETAILED_VAL to (1U)	FSBL_DEBUG_DETAILED

On what all processor cores can FSBL run on?

FSBL can only be run from A53_0 (AArch32 and AArch64), R5_0, R5_Lockstep

What part of OCM is used past FSBL?

OCM region used by FSBL: 0xFFFC0000 – 0xFFFE9FFF. The terminal 512 bytes of this region is used by FSBL to share the handoff parameters corresponding to applications ATF hands off. FSBL fully uses this OCM region and, in fact, in sure designs and when certain features need to enabled, the electric current footprint of FSBL doesn't fit in this available OCM. For details, search for "footprint" in this wiki.
ATF uses the rest of OCM i.e. from 0xFFFEA000 to 0xFFFFFFFF. Please note that the current implementation of APU-only restart assumes that FSBL "resides" in OCM fifty-fifty afterwards its execution is complete. This is since, in such scenarios, PMUFW easily off to (already existing) FSBL without really restarting.
Hence, OCM is completely used between FSBL and ATF and with the available APU-only restart machinery, no other awarding can reuse it.

How is xfsbl_translation_table.S dissimilar from translation_table.S of BSP?

xfsbl_translation_table.South is a re-create of file translation_table.S (of A53). The divergence is that the FSBL's copy of this file marks DDR region as reserved. This is to avert speculative access to DDR earlier information technology is initialized. One time the DDR initialization is washed in FSBL, retentivity attributes for DDR region is inverse to "Memory" and then that information technology is cacheable.

What ECC initialization is done by FSBL?

TCM ECC Initialization: When FSBL runs on R5, TCM ECC is e'er initialized. Also, when FSBL loads awarding targeted on R5, the corresponding TCM'due south ECC is initialized. When FSBL runs on A53, by default, TCM ECC is non initialized every bit this as well involves powering up of RPU. In such cases, TCM ECC Initialization can be performed by defining FSBL_A53_TCM_ECC_EXCLUDE_VAL to 0 in xfsbl_config.h.
DDR ECC Initialization: Washed in FSBL if ECC for DDR is enabled in design.

FSBL provides pick to enable/disable certain features from building. By selectively disabling certain features every bit mentioned in below tabular array, code size can be reduced. These flags are divers in xfsbl_config.h of FSBL.

FLAG	default value	Meaning of default setting / Notes	Significant impact on FSBL size?
FSBL_NAND_EXCLUDE_VAL	(0U)	NAND Boot mode related code is included (if NAND is present in design)	Yep
FSBL_QSPI_EXCLUDE_VAL	(0U)	QSPI Kick manner related code is included (if QSPI is present in design)	Yes
FSBL_SD_EXCLUDE_VAL	(0U)	SD Kick mode related code is included (if SD is present in design)	Yes
FSBL_SECURE_EXCLUDE_VAL	(0U)	Secure features (Authenctication and decryption) are enabled	Aye
FSBL_BS_EXCLUDE_VAL	(0U)	PL Bitstream load adequacy is enabled	Yeah
FSBL_SHA2_EXCLUDE_VAL	(1U)	SHA2 is non supported	Aye
FSBL_EARLY_HANDOFF_EXCLUDE_VAL	(1U)	This flag/characteristic is not fully supported and hence is not recommended to change this setting	No
FSBL_WDT_EXCLUDE_VAL	(0U)	Watchdod timer feature is included	No
FSBL_PERF_EXCLUDE_VAL	(1U)	Functioning prints are not shown by default	No
FSBL_A53_TCM_ECC_EXCLUDE_VAL	(1U)	TCM ECC is non initialized for A53 ALWAYS. Changing this flag volition result in TCM ECC being initialized always.	No
FSBL_PL_CLEAR_EXCLUDE_VAL	(1U)	PL Initialization/clearing volition be done ONLY when the boot image has PL bitstream. Changing this volition outcome in PL Initialization/immigration to be washed ALWAYS during FSBL Initialization	No
FSBL_USB_EXCLUDE_VAL	(1U)	USB Slave boot way back up is disabled	Yes
FSBL_PROT_BYPASS_EXCLUDE_VAL	(1U)	Past default (from 2018.1), complete XMPU/XPPU configuration is done. Changing this flag volition result in FSBL bypassing XPPU and FPD XMPU configuration and isolation/protection characteristic will exist just limited to OCM slave.	No
FSBL_PARTITION_LOAD_EXCLUDE_VAL	(0U)	By default FSBL loads all the partitions in the image, if this macro is been set, FSBL skips the partitions loading and will run the way it runs in JTAG boot mode.
FSBL_FORCE_ENC_EXCLUDE_VAL	(0U)	By default FSBL forces encryption of all the partitions when ENC_ONLY flake is blown, but if this macro is been set encryption can be optional for all the partitions loaded by FSBL, yet information technology is compulsory for FSBL partitioning.
FSBL_UNPROVISIONED_AUTH_SIGN_EXCLUDE_VAL	(1U)	By default the lawmaking to load authenticated partitions as non-secure when RSA_EN eFUSE is non programmed is excluded. If changed to "0", an authenticated paradigm tin boot equally not-secure when RSA_EN eFUSE is not programmed.

Debug prints: By default only FSBL imprint is printed. If more than debug prints are enabled, these will result in use of more retentiveness.
Drivers Asserts: Asserts are used inside all Xilinx drivers and can be turned off on a arrangement-wide basis by defining, at compile time, the NDEBUG identifier (calculation –DNDEBUG confronting extra_compiler_flags of drivers). This will help further reduce FSBL footprint.

I'1000 unable to debug FSBL in Vitis. Whatever change in optimizations used by FSBL?

Starting in 2019.two, the FSBL will be built with –Os and LTO optimizations by default in VITIS. This prevents the view of C lawmaking in the debugger.

To be able to view the C lawmaking during debug, these are few options:

Disable Optimization flags AND exclude unused FSBL code.
1. In the "Miscellaneous" Section of FSBL app, remove highlighted options below.

This would make the FSBL as well big to exist able to fit in OCM and continue with debug. Brand sure that EXCLUDE flags options are enabled in"xfsbl_config.h" if a feature is not used and can be excluded. If that doesn't free up plenty space, the second option (of reducing optimization) tin be looked at and followed.

Reduce/Change the level of Optimization.
1. Modify the flags to remove "-Bone -flto -ffat-lto-objects" and include only "-O1" (optimization for lawmaking size and execution time) instead.
2. If doing the in a higher place doesn't work and "-O1" is yet hard to debug, modify flags to remove "-Bone -flto -ffat-lto-objects" and include "-Og" instead. "-Og" stands for Optimized Debug Experience. To exist used along with this, some of the optimization flags can be tried manually. "-Og -finline-functions-chosen-once" is known to have worked.

REFERENCE: For more info on optimization: https://gcc.gnu.org/onlinedocs/gcc-8.2.0/gcc/Optimize-Options.html#Optimize-Options

Of import NOTE: The following zynqmp_fsbl_bsp flag need to exist inverse to Simulated after removing or reducing the optimization (either of the 3 methods to a higher place).

This will avoid turning back-on of the FSBL BSP optimization during rebuilding .

What are the memory regions and registers reserved for FSBL?

Post-obit are the retention regions and registers reserved for FSBL:

DDR region - 0x100000U (XFSBL_DDR_TEMP_ADDRESS) → This is the address in DDR where bitstream will be copied temporarily.
DDR region - 0x4000000U (XFSBL_DDR_TEMP_BUFFER_ADDRESS) - This is the address in DDR where kick prototype will be copied in USB boot mode.
0xFFD80034 (PMU_GLOBAL_GLOBAL_GEN_STORAGE2) → Since 2018.1 if POS is enabled, FSBL waits till PMU has finished resuming by polling this register. Users are free to utilise this annals after reset so information technology tin can all the same exist considered as "reserved for customers".
0xFFD80038 (PMU_GLOBAL_GLOBAL_GEN_STORAGE3) → Since 2018.i if POS is enabled, PMU waits till FSBL has finished reading the boot type. This additional handshake footstep is required in kicking scenarios where FSBL is started by CSU. PFW must wait for CSU to trigger FSBL offset otherwise at that place may be race status where PFW is trying to restore state of processor as role of resume from Power Off Suspend sequence while CSU is trying to run FSBL on that aforementioned processor. Users are costless to use this register after reset so it tin still exist considered as "reserved for customers".
0xFFD80040 (PMU_GLOBAL_GLOBAL_GEN_STORAGE4 - $.25 1 and 2) → Since 2018.3, these bits are used to know the status of RPU 0 and RPU 1 usage which will be updated by FSBL. Based on this information, PMU volition decide whether to shutdown the unused RPU cores or not.
0XFFD80040 (PMU_GLOBAL_GLOBAL_GEN_STORAGE4 - bit 16) → Written past PMUFW, FSBL uses this annals to know if reset is APU only reset.
0XFFD80044 (PMU_GLOBAL_GLOBAL_GEN_STORAGE5 - chip 0) → Written by FSBL, PMU Firmware uses this register to know if FSBL has completed its execution. Since 2018.one, this check is performed to initialize and start the CSU WDT timer when ENABLE_WDT macro is defined.
0XFFD80044 (PMU_GLOBAL_GLOBAL_GEN_STORAGE5 - bits one and ii) → Written past FSBL. PMU Firmware uses these bits to know if FSBL is running on which processor. 01: APU, x: RPU0, 11: RPU LS
0XFFD80048 (PMU_GLOBAL_GLOBAL_GEN_STORAGE6) -> FSBL writes to this register the address from where ATF can read the details of partitions to which ATF has to handoff
0XFFD80060 (PMU_GLOBAL_PERS_GLOB_GEN_STORAGE4) → For error reporting in FSBL
0xFFD8006C (PMU_GLOBAL_PERS_GLOBAL_GEN_STORAGE7 - bit 4) → Since 2018.3, FSBL is using this bit to betoken DDR clock set up.

PMU Firmware also uses few general storage registers. Please refer to this link in PMU Firmware wiki for the list of registers reserved for PMU Firmware

Is there any society in which I take to specify bitstream in BIF file (for boot image creation)?

Yeah, from 2017.one release. Bitstream should exist loaded before ATF is loaded. The reason is FSBL uses the OCM region which is reserved for ATF for holding a temporary buffer in the case where bitstream is nowadays in .BIN file. Because of this, if bitstream is loaded after ATF, FSBL will overwrite the ATF image with its temporary buffer, corrupting ATF image. Hence, bitstream should exist positioned in .BIF before ATF and preferably immediately subsequently FSBL and PMUFW.

I could come across that USB boot mode support is added in FSBL but is disabled past default. Why?

USB kick fashion support increases the footprint of FSBL further (by ~10KB). Since it is intended by and large during initial evolution phase, its back up is disabled by default to conserve OCM space. Delight refer "I'm unable to build FSBL due to size issues, how can I reduce its footprint" department for details on how to reduce memory foot impress of FSBL.

What board specific configuration is washed in FSBL?

FSBL should exist generic and ideally should be free from any board specific configuration. Nonetheless, for the ease of development, certain lath specific initialization is done in XFsbl_BoardInit() in which below are done:

Feature applicability board wise	ZCU102	ZCU106
GT configuration for ZCU102 board	Yes	No
Reset to Precious stone	Yes	Yes
Enabling FMC ADJ	Yeah	Yes
USB reset (CRL_APB_BOOT_PIN_CTRL)	Yes	Yes
PCIe reset (GPIO_DATA_1 register)	Yes	No

What is early handoff and does FSBL support this?

FSBL loads the partitions one after other and once loading of all partitions is complete, handing off to CPUs of corresponding partitions is done past FSBL. Early handoff is a scenario where a division is handed off immediately subsequently its loading into memory. This feature can exist useful when an (due east.g. RPU) awarding needs to be started as early equally possible after its loading.
This characteristic (for R5 partitions) was supported by FSBL in earlier releases. The corresponding code in FSBL is notwithstanding present but this feature is no more being supported in FSBL. This is since, Isolation will be enabled in FSBL while handing off (kickoff/early on). This can create problem when loading of further partitions (accessing of retention, CSU).

What are various handoffs supported (between AArch32, AArch64, different cores)?

Below table shows various combinations of handoffs supported in FSBL:

FSBL	Application	Processor cores	Execution address
64-chip	64-fleck	All (i.e. A53-0, A53-1, A53-ii, A53-3)	Whatever accost
64-flake	32-fleck	A53-1, A53-ii, A53-3	0x0
32-flake	32-flake	A53-0	Whatever accost
32-bit	32-bit	A53-i, A53-2, A53-iii	0x0
32-flake	64-bit	A53-1, A53-two, A53-iii	Any address

What are the diverse hooks provided in FSBL code?

Hooks are functions which can be divers by users. FSBL provides blank functions, and calls them from certain strategic locations. Below are the hooks bachelor currently:

Hook purpose/location	Hook office proper noun
Before PL bitstream loading	XFsbl_HookBeforeBSDownload()
After PL bitstream loading	XFsbl_HookAfterBSDownload()
Before (the first) Handoff (to whatever application)	XFsbl_HookBeforeHandoff()
Earlier fallback	XFsbl_HookBeforeFallback()
To add more initialization lawmaking, in improver to that in psu_init or to replace psu_init with custom initialization	XFsbl_HookPsuInit(()

How boot time measurements can be done in FSBL?

Kick time (or performance) measurement is a way to mensurate fourth dimension taken to consummate sure fourth dimension consuming activities (e.yard. partition copy, authentication, decryption etc). In addition, overall time taken past FSBL (measured from after psu_init completion to completion of all partitions/bitstream loading) is likewise provided. This feature can be enabled by defining macro FSBL_PERF_EXCLUDE_VAL (in xfsbl_config.h) to 0. Debug prints should not exist enabled when p

What is Secondary Kicking mode?

There is a provision to have two boot devices in the Zynq UltraScale+ MPSoC architecture. The primary boot mode is the boot mode used by BootROM to load FSBL and optionally
PMU FW. The secondary kick style is the boot device used by FSBL to load all the other partitions. The supported secondary boot modes are QSPI24, QSPI32, SD0, eMMC, SD1,
SD1-ls, NAND and USB. By default, secondary kicking device is the same equally primary boot device unless explicitly mentioned using boot_device param in the bif file.

A secondary boot device can be specified in the bif file as [boot_device] qspi24. This implies that FSBL would be loaded from the master boot device but all other partitions will be loaded from the secondary kicking device qspi24. Secondary boot requires and two bif files and hence two boot images. The first bif contains the partitions loaded by BootRom and also the "[boot_device] qspi24"argument specifying the secondary boot mode. The second bif file contains the FSBL sectionalization followed past all the partitions to exist loaded by FSBL.
"bootgen -bif_help boot_device" will listing all the secondary boot options.

If secondary boot mode is specified, it should be different from the main boot device. For example, if QSPI32 is the main kicking way, QSPI24 cannot be the secondary kick mode. Instead, yous can have SD0, eMMC, SD1, SD1-ls, NAND, USB every bit secondary kick modes. All combinations of boot devices are supported as principal and secondary boot devices.

Attached are sample bif files for master and (usb as secondary) boot modes:

boota53_all.bif

What are the peripherals/IPs required for FSBL?

CSUDMA, ADMA_0 and any 1 instance of IPI are required IPs for FSBL. In addition, for ZCU102 and ZCU106 boards, I2C0 is needed for board-specific configuration washed in FSBL. Hence these IPs are required in pattern and also should be not isolated from the processor for which FSBL is being created.

Revision History

What's new in 2021.2 release?

Added Winbond flash support to ZynqMP FSBL
Added MultiDie read support for Micron 2Gb wink role
Fixed logical consequence in Secondary boot mode

What's new in 2021.1 release?

Fixed secure boot event in USB boot mode
Added FSBL_UNPROVISIONED_AUTH_SIGN_EXCLUDE_VAL macro to xfsbl_config.h, if this macro is set to 0 (set to 1 past default), authenticated images would boot as non secure images if RSA_EN is non programmed
Added XFSBL_PL_LOAD_FROM_OCM macro to xfsbl_config.h, if this macro is enabled (disabled by default),bitstream would become loaded from OCM even if DDR is present in design

What'due south new in 2020.2 release?

Removed SHA2 related references from sw_apps and sw_services
Removed checksum related code out of secure code
Fixed upshot in USB boot mode

What'due south new in 2020.ane release?

FSBL updates PMU GLOBAL register to indicate PL configuration
Update the status of FSBL image encryption in fleck iii of PMU_ GLOBAL_GLOBAL_GEN_STORAGE5
Added support for ZCU216 and ZCU208 boards
FSBL considers high DDR addresses for R5
Added Macronix 2G flash support to FSBL

What'south new in 2019.ii release?

Added support for RPU only subsystem restart case

What's new in 2019.one release?

Added dual parallel configuration support and QPI back up for 24bit qspi boot fashion for Macronix flash parts
AES engine and SHA engine are reset during FSBL initialization
Zeroize PL upon error in decryption
Removed sha2 support from FSBL
Ever select EEPROM lower folio for reading SPD data
Dynamic DDR configuration is strictly based upon the design for all boards including ZCU102 and ZCU106
Added back up for armclang compiler
Removed disabling of the WDT error before exiting FSBL to avert overwriting of the PMU settings
Updated PMU with FSBL running status using bits 1 and 2 from PMU global general-purpose annals 5
DDR terminate address is not stock-still at 2GB but derived from Vivado
Using XilPM XPm_SetConfiguration API instead of using direct IPI calls for communicating with PMUFW.

What's new in 2018.2 release?

Added power to read FMC EEPROM and set VADJ voltage for ZCU104 boards
Added back up for enhanced user fuses revocation for secure boot

What's new in 2018.one release?

Isolation fully enabled in FSBL
Added support for NIST-SHA3 padding
Added Boot header authentication
Forcing encryption for all partitions when ENC_ONLY eFUSE fleck is set
Fixed AES KEY and IV re-apply vulneribility outcome
Added back up to exclude segmentation loading
Added alarm prints in case PMU-FW is not running
Added support for Macronix 1.8V flash
Added support to brand FSBL wait for PMU to observe kick blazon

What's new in 2017.4 release?

Added functionality in FSBL to distinguish EV devices from EG devices

What's new in 2017.three release?

Secondary kicking style support added
- Supported secondary boot modes: QSPI24, QSPI32, SD0, SD1, eMMC, SD1-LS, USB, NAND.
QSPI 1-fleck and ii-bit support added

PMU Firmware : http://www.wiki.xilinx.com/PMU+Firmware

ane) XFSBL_PL_PWRUP_WAIT_MICROSEC macro added to provide wait time for PL to power up. The default value is naught but customers can fix it as per their requirements.